Packaging and Hybrid Integration
‘Breaking the packaging cost barrier’
The Packaging and Hybrid Integration theme will focus on the high cost of photonic packaging, which can amount to as much as 80% of total product cost in some applications, which has restricted the deployment of photonics to a relatively small number of mass and niche markets to date (albeit markets of enormous value).
The research in the IPIC Packaging Theme concentrates on materials, processes and technologies that reduce the cost of photonic device assembly and packaging. The goal is to shift from the current state-of-the-art methods of singulated photonic-integrated chip (PIC) packaging into wafer-level approaches that are the gold standard in electronic industry. These will enable surface-mounted and pluggable solutions for variety of photonic-enabled markets – from telecommunications to LIDAR and biomedical.
Research Topics
On-PIC Thermo-Electric Coolers
Area: Material Science, Thermodynamics, Wafer-Level Processing
In contrast with electronics, which can work comfortably in a wide range of temperatures, many photonic devices are sensitive to temperatures, e.g. laser efficiency decreases with temperature. Additionally some passive components on the PIC, e.g. ring resonators, require precise temperature regulation and adjustment. This is currently achieved using local heat sources (resistors), while the cooling is delivered using a large thermo-electric cooler (TEC) that sits below the PIC and therefore cools the entire chip. In most cases this increases the cost of operation of the device [1].
The solution proposed by IPIC is integrated micro-TECs, providing local heating and cooling capacity to the active or passive on-PIC components. This involves growing thermoelectric materials (i.e. materials with non-zero Seebeck coefficient) directly onto Si. These can be then integrated either directly onto the device or prepared separately and flip-chipped onto the wafer. Another aspect of the research involves improving the efficiency of the micro-TECs, especially the efficiency of p and n-type materials, as their cooling power depends on the efficiency of these thermoelectric materials [2, 3].
[1] K. Gradkowski, C. Eason, J. S. Lee, S. Bernabe, E. Temporiti, L. Carroll, P. O’Brien, Thermal Challenges for Packaging Integrated Photonic Devices, 2016 6th Electronic System-Integration Technology Conference (ESTC).
[2] S. Lal, K. M. Razeeb, D. Gautam, Enhanced Thermoelectric Properties of Electrodeposited Cu-doped Te films, ACS Applied Energy Materials 3(4), 3262 (2020).
[3] S. Lal, D. Gautam and K. M. Razeeb, Fabrication of micro-thermoelectric devices for power generation and the thermal management of photonic devices, J. Micromech. Microeng. 29, 065015, 2019.
Wafer-Level Interposers
Area: Material Science, Thermodynamics, Surface-Mounted Photonics
Increasingly, modern devices require high levels of integration of photonic and electronic components, especially in the area of high-speed telecommunications. This is done by using Silicon interposers that mediate electrically between the electronic and photonic chips. However, unlike electronics, PICs are frequently temperature-sensitive, while the electronics tend to run very hot. Therefore at high levels of integration, there is large thermal-crosstalk (Silicon is good thermal conductor) which increases cooling requirements of the entire device.
The solution proposed is to substitute Silicon with a glass interposer. Besides small thermal conductivity that limits cross-talk, it has other advantages. It is easier and cheaper to process than Silicon and is compatible with 3D writing techniques. High-speed transmission lines can be integrated with small pitch as well due to high dielectric constant of glass (however not as high as Silicon). Its’ small thermal conductivity is detrimental in that the heat cannot be now easily removed from the PIC and thermal control is made more difficult. However, glass easily allows etching of vias that can, when filled with metal, act as thermal conduits for heat extraction, as well as electrical interconnects. Such-designed glass interposer can be a wafer-level platform for high-level integration of photonic packages.
Pluggable Micro-Optics
Area: Optics, Surface-Mounted Photonics, Pluggable Photonic Devices
In the current state-of-the-art of photonic packaging the fibre (or fibre array) is attached directly to the photonic chip to facilitate optical I/O. This is a very precise and laborious process, which is difficult to scale. These increase the price of the packaged photonic device. In order to follow the footsteps of the electronic revolution, photonics needs to become compatible with pick-and-place surface-mounting techniques that electronics has perfected for decades.
The proposed solution is to substitute the permanent connection between the PIC and fibre with a pluggable one [4]. This will allow the photonic chip to be placed in the package separately, with the optical fibre connection being delivered independently afterwards. This will reduce the complexity of the packaging process, leading to faster turnaround and reduced cost.
In order to facilitate a pluggable connection, IPIC research will focus on micro-optic arrays at the optical interface. The goal is to relax the tolerances of alignment of the connector by increasing the beam waist and collimating it. Increasing tolerances by a factor of 5-10 brings packaging into the range of cost-effective machining techniques that allow for pluggable connections. Research will focus on designing the micro-optic arrays, compatible with existing PIC couplers and methods of wafer-level attachment to the PICs.
[4] C. Scarcella, K. Gradkowski, L. Carroll, J-S. Lee, M. Duperron, D. Fowler, P. O’Brien, Pluggable Single-Mode Fiber-Array-to-PIC Coupling Using Micro-Lenses, IEEE Photonics Technology Letters 29, 1943 (2017).
